The present invention relates to a high-speed, low-power-consumption, low-noise semiconductor device.
Attention has heretofore been given to BiCMOS technology as means for operating the semiconductor devices at high speeds as disclosed in Nikkei Microdevice, Feb., 1988, pp. 52-84.
As is well known, the BiCMOS technology is the one in which a bipolar transistor and a CMOS are combined together in an elementary circuit or on the same chip. This technology is intended to increase the operation speed of an LSI by utilizing higher driving capability of the bipolar transistor while maintaining the high-density and low-power characteristics comparable with that of the CMOS circuits.
According to the conventional BiCMOS technology, however, the operation speed can be doubled at the greatest compared with that of the CMOS circuits. Therefore, in order to use, for example, a dynamic random access memory (DRAM) together with the currently employed MPU [MC 68020 (trade name, Motorola Co. in U.S.A.)] having an operating frequency of 20 to 30 MHz or together with [A 80386 (trade name, Intel Co. in U.S.A.], the access time must be shorter than 50 ns. The access time will have to be further shortened in the future. However, the BiCMOS DRAM based on the conventional BiCMOS technology imposes limitation with regard to the operation speed. Therefore, the existing BiCMOS technology is no longer capable of further improving performance of information processing equipment.
In recent years, furthermore, LSI's with mixed analog-digital functions have been vigorously developed, and attention has been given to the BiCMOS technology which uses small signal detecting capability of the bipolar transistor for such LSI's. With the conventional BiCMOS technology, however, the signal amplitude of the BiCMOS circuit in the digital unit is nearly equal to a supply voltage (e.g., 5 volts), i.e., the signal amplitude of the BiCMOS circuit is great. Moreover, since the rising/falling time of the signal is very short, noise voltage is induced in the power supply lines and in the neighboring signal lines which are coupled to an analog unit that handles small signals to impair stability in the operation.
This is because the input and output signals of a number of BiCMOS circuits constituting the BiCMOS LSI have a large amplitude which is nearly the same as the supply voltage. This can be solved effectively if the amplitude of internal signals is decreased. For instance, an input signal of the ECL level from a unit outside the chip is received by a current switching circuit of a bipolar transistor to generate a signal of an amplitude of 0.8 V to 1.6 V. This signal is used to operate most of the internal circuits such as decoder circuits and like circuits such that the chip as a whole operates at high speeds suppressing noise. In, for example, the DRAM and SRAM, however, signals of a large amplitude are needed to drive the word lines of memory cells. In order to convert the level in the decoder or the word driver, therefore, it is necessary to use a level converter circuit that operates at high speeds yet consuming small amounts of electric power.